In some computing systems, low level instruction code is used as an intermediary between the hardware components of the computing system, the operating software, and other high level software executing on the computing system. In some computer systems, this low level instruction code is known as the computer Basic Input and Output System (“BIOS”). The BIOS provides a set of software routines that allows high level software to interact with the hardware components of the computing system using standard calls.
Because of limitations of the BIOS in many PC-compatible computers, a specification for creating the firmware that is responsible for booting the computer and for intermediating the communication between the operating system and the hardware has been proposed. The specification is called the Extensible Firmware Interface (“EFI”) specification and is available from INTEL CORPORATION. The original EFI Specification from INTEL CORPORATION has also been extended by the Unified Extensible Firmware Interface (“UEFI”) Forum. Additional details regarding the EFI and UEFI firmware architectures are defined by the group of specifications called INTEL Platform Innovation Framework for EFI (“the Framework”), which is available from INTEL CORPORATION.
The EFI specification describes an interface between the operating system and the system firmware. In particular, the EFI specification defines the interface that platform firmware implements, and the interface that the operating system can use in booting. How the firmware implements the interface is left up to the manufacturer of the firmware. The EFI specification provides protocols for EFI drivers to communicate with each other, and the core provider functions such as allocation of memory, creating events, setting the clock, and the like. This is accomplished through a formal and complete abstract specification of the software-visible interface presented to the operating system by the platform and the firmware.
Both BIOS and EFI utilize the system management mode (“SMM”) provided in microprocessors available from INTEL CORPORATION and AMD CORPORATION. SMM is a special-purpose operating mode for handling system-wide functions like power management, system hardware control, or proprietary original equipment manufacturer (“OEM”)-designed code. A benefit of SMM is that SMM can offer a distinct and isolated processor environment that operates transparently to the operating system or executive and software applications.
When SMM is invoked through a system management interrupt (“SMI”), the central processing unit saves the current state of the processor (the processor's context), then switches to a separate operating environment contained in a special portion of random access memory (“RAM”) called the system management RAM (“SMRAM”). While in SMM, the microprocessor executes SMI handler code to perform operations such as powering down unused disk drives or monitors, executing proprietary code, or placing the entire computer in a suspended state. When the SMI handler has completed its operations, the SMI handler executes a resume (“RSM”) instruction. This instruction causes the microprocessor to reload the saved context of the processor, switch back to protected or real mode, and resume executing the interrupted application or operating-system program or task. Operating systems (“O/S”) and applications executing at the O/S level utilize software SMIs to invoke firmware services. For example, the O/S and applications can utilize software SMIs to invoke services provided by the BIOS or other type of computer system firmware.
In some examples, it may be desirable for certain functions to occur prior to handing over a system to a primary O/S after firmware initialization. In conventional systems, to provide for that functionality, the initialization of the primary O/S may be interrupted, whereby the initialization for a secondary O/S commences. Once the secondary O/S is shut down, the initialization procedure of the primary O/S is restarted.
It is with respect to these and other considerations that the various configurations described below are presented.